The present invention relates generally to a digital link such as a differential bit link, which may be part of a multi-bit link between two chips. In particular, it relates to methods and circuits for supplying power to one or more transmitters in a link.
FIG. 1 generally shows a conventional transceiver with a transmitter (Tx) 102 and receiver (Rx) 104 coupled to a channel 101 to be linked with a corresponding transceiver at the other side of the channel, e.g., on a different chip. The receiver 104 comprises both current mode logic (CML) and CMOS (complementary metal oxide semiconductor) signal conditioning logic, as does the transmitter 102. The transmitter 102 also has a current mode output driver circuit to drive a transmitted signal over the channel 101. A global Vcc supply 103 supplies the CMOS and CML circuits (including the output driver) with their supply voltages.
A global CML IBias supply 107 provides the CML signal-conditioning logic with a current bias signal (ILBias), and a current bias source 105 for the driver in the transmitter provides to the driver a current bias signal (IDBias). The driver bias signal primarily affects the output swing of the transmitter, while the voltage supply (Vcc) and CML bias current (ILBias) primarily affect the data rate capabilities for the transmitter and receiver.
With power consumption continuing to be an important consideration, new approaches to providing these supplies and/or bias signals may be desired.